This invention relates to a differential amplifier comprising a first and a second transistor having collectors coupled to a common terminal by means of a load and having their mutually coupled emitters coupled to a first supply-voltage terminal via a first resistor and a first current source and via a second resistor and a second current source. The coupled emitters are also coupled to the emitter of a third transistor via said first resistor. The third transistor has its base coupled to the base of the first transistor and to a first input terminal. The coupled emitters are further coupled to the emitter of a fourth transistor via said second resistor. The, which fourth transistor has its base coupled to the base of the second transistor and to a second input terminal.
Such a differential amplifier can be used in integrated semiconductor circuits and, in particular, in fast analog-to-digital converters, operational amplifiers and sample-and-hold circuits.
Such a differential amplifier is known from U.S. Pat. No. 4,616,190. In this known amplifier the first and second transistor form a differential pair to which the emitter currents are supplied by the first and the second current source via the first and the second resistor. The third and fourth transistor, together with the first and the second resistor, constitute an emitter-degenerated differential pair whose bias currents are also supplied by the first and the second current source. The collectors of the first and the second transistor are each coupled to a second supply voltage terminal via a resistor and the collectors of the third and the fourth transistor are connected directly to this supply-voltage terminal. The output signal is taken from the collectors of the first and the second transistor. In the balanced state, in which the voltage difference between the input terminals is zero volts, the currents through the first and the second transistor are substantially equal to each other, which is also the case with the currents through the third and the fourth transistor. In the case of a positive voltage difference between the first and the second input terminal the currents through the first and the third transistor increase and the currents through the second and the fourth transistor decrease. The current increase is provided by the second current source via the second resistor. If the input voltage increases the second transistor will be cut off first. The fourth transistor remains conductive for the time being so that the current through the first transistor can still increase via the second resistor. In this way the driving range of the first transistor is extended, until the fourth transistor is also cut off. A similar response is obtained if the input voltage has the opposite polarity. Since the voltage between the output terminals and the first supply voltage terminal should always be adequate to allow a correct operation of the intermediate elements, the two output potentials can never become equal to said supply voltage. However, the output voltages can become equal to the voltage on the second supply voltage terminal. This results in a class AB behaviour of the output voltages, which do not intersect in the centre of the output characteristic. A single-ended class A output signal, for which the balanced state is situated in the centre of the output characteristic, can be otained only if the load is constituted by a current mirror.